The field effect transistor (FET) is a three terminal device in which the current through two terminals is controlled by the voltage at the third terminal. FETs are used in many electronic devices, from computer systems to communications systems. FETs can be divided into two main classes, n-type and p-type. n-type or p-type refers to the doping type of the channel region. Thus, a p-type FET or pFET comprises p-type source region, drain region, and channel, and n-type gate regions.
In some applications, the drain signal will originate from a chip that is different from the origination of the source and gate signals. For example, the FET may be located on a receiver chip, and is the intended termination of signals from a driving chip. Thus, it will sink a certain amount of current, depending on the voltage of the incoming signal VM. Since the signals may be on different chips, the FET power signal may be off, while the driving signal may be on. This can cause problems for both the FET resident, receiving chip and the driving chip.
An schematic example of a pFET is shown in FIG. 4A. A physical arrangement of a PFET is shown in FIG. 4B. FET 40 includes source 41 connected to VDL, drain 42 connected to VM, control gate 45 which is connected to a control signal, here GND, and substrate gate 43 which is tied to VDL. Substrate gate 43 could be an n-well in a p-type substrate, or it could be a portion of a n-type substrate. In operation, FET 40 uses a p-type channel 44, which is controlled by control gate 45. When control gate 45 is at ground, channel 44 is open and allows current to flow. When gate 45 has voltage greater than source 41 minus the pFET threshold voltage, then channel 44 is pinched off and current flow from source 41 to drain 42 is prevented. Thus, gate 45 controls the flow of current by application of the voltage in the gate signal.
A problem occurs when the resident chip of FET 40 loses power, and VDL at source 41 drops to ground. When this occurs, a pn diode is formed between drain 42, which is p-type, and n-type substrate gate 43. Drain 42 receives VM which is the signal from the driving chip. If VM is a positive voltage of greater than approximately 0.7volts, or the threshold activation voltage of the pn diode, then the pn diode turns on and sinks a large amount of current from source 42 to substrate gate 43. This occurs because the substrate is no longer biased at the power supply voltage, it is now held at ground.
Note that the diode provides a very low resistance path to ground, thus this appears to be a short circuit to the driving chip from a transmission perspective. If the VM signal is not terminated with the correct impedance, it will cause a reflection wave back to the driving chip, at nearly full value of voltage. Since the diode appears as a short circuit, the reflection signal will reflect back with a negative or inverse wave (an open circuit would reflect a positive wave). The negative wave could cause interference, either constructive or destructive, depending upon the phases of the signals. Constructive interference may result in a signal that exceeds the capabilities of the driving chip and damage the chip, whereas destructive interference may result in degradation of the signal sent to the receiving chip.
The large amount of current flow causes the driving chip to have to supply a lot of current. Moreover, the large current generates a large amount of heat in both the driving chip and the receiving chip. The current flow to the receiving chip could also charge up the substrate of the receiving chip, as if the receiving chip were a capacitor. During power up of the receiving chip, or otherwise grounding the charged substrate, the stored current would discharge and may damage the receiving chip.
Current also flows from VM to VDL. When VDL is at power off ground, and gate 45 is also at ground, then FET 40 is still in the saturation region and current flows through the source to ground from the drain, as channel 44 is still open. So this is another current flowing through the FET when the power is down on the receiving chip. Moreover, this additional current must also be provided by the driving chip. Note that this current flow will also cause signal reflection, as the current flow will result in improper impedance matching, and hence reflection.
Both current sinking mechanisms, i.e. the draining from the pn diode and the drain through the channel, together draw approximately 1.6 amps. This is much larger than the normal power up driving current of 72 ma. Thus, a power off condition of the receiving chip places a very tough current demand for the driving chip power supplies to meet.
Note that the problems described herein only occur with a pFET, and not a nFET. With a nFET, a np diode would be formed, which will not turn on from a voltage at the drain. Moreover, the gate of the nFET would have to be connected to VDL in order for the nFET channel to be open, and upon power loss would go to ground, and thus pinch off the channel.
Therefore, there is a need in the art for a mechanism which will prevent current flow from the drain to the source and substrate, in a power off condition of a p-type FET.